Recently, there has been considerable interest in the potential of field-effect transistors (FETs) using III-V semiconductor materials for advanced logic applications. See R. Chau, B. Doyle, S. Datta, J. Kavalieros, and K. Zhang, “Integrated Nanoelectronics for the Future,” Nature Materials 6, 810-812 (2007); and J. A. del Alamo, Nature 479, 317-323 (2011). A high-speed, low-power logic technology utilizing such III-V materials could enhance digital circuit functionality and sustain Moore's law for additional generations. When utilized in mixed-signal circuits, such materials can also enable a significant reduction in power consumption.
For these applications, complementary circuits based on n- and p-channel FETs would be highly desirable due to their low-power, high-speed advantages. A key issue is the composition of the channel and barrier materials for both the n-FET and the p-FET. A strong candidate for the n-FET is a high-mobility InGaAs channel clad by InAlAs barriers. This can take advantage of the mature InP high-electron-mobility transistor (HEMT) technology—so named because InP is usually used as a substrate for lattice-matched or strained InGaAs and InAlAs. Integrated circuits based on InP HEMTs are used in a variety of microwave applications including cell phones, cellular base stations, fiber optic systems, radar, radio astronomy, and satellite communications. See J. A. del Alamo, “The High Electron Mobility Transistor at 30: Impressive Accomplishments and Exciting Prospects,” CS Mantech Proc., 17-22 (2011).
Quantum wells of InGaAs/InAlAs have a sufficient valence band offset for hole confinement, and so one CMOS option is to combine InGaAs p-FETs and n-FETs. A few groups have investigated p-type modulation doped InGaAs/InAlAs QWs, but the hole mobilities in such materials are only 200-400 cm2/V s at room temperature, which will limit the performance of InGaAs p-FETs. See A. M. Kusters, A. Kohl, V. Sommer, R. Muller, and K. Heime,” Optimized double heterojunction pseudomorphic InP/InxGa1−xAs/InP (0.64×0.82) p-MODFETs and the role of strain in their design,” IEEE Transactions on Electron Devices 40, 2164-2170 (1993); P. Nagaiah, V. Tokranov, M. Yakimov, and S. Oktyabrsky, “Strained Quantum Wells for p-Channel InGaAs CMOS,” Performance and Reliability of Semiconductor Devices MRS Proc. 1108, 231-236 (2009); T. J. Drummond, T. E. Zipperian, I. J. Fritz, J. E. Schirber, and T. A. Plut, “p-channel, strained quantum well, field-effect transistor,” Applied Physics Letters 49, 461-463 (1986); and M. Kudo, H. Matsumoto, T. Tanimoto, T. Mishima, and I. Ohbu, “Improved hole transport properties of highly strained In0.35Ga0.65As channel double-modulation-doped structures grown by MBE on GaAs,” Journal of Crystal Growth 175, 910-914 (1997). In contrast, mobilities greater than 2000 cm2/V s have been achieved for strained Ge/SiGe QWs. See M. L. Lee, E. A. Fitzgerald, M. T. Bulsara, M. T. Currie, and A. Lochtefeld, “Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors,” Journal of Applied Physics 97, 011101 (2005). Consequently, a second option is to combine InGaAs n-FETs with Ge p-FETs. See J. A. Del Alamo, supra. Integration is a challenge with this approach, however, because of the different crystalline structures and lattice constants for the two material systems.
The use of antimonide-based materials for both the n- and p-channels is also an attractive possibility, since they have excellent electronic properties and may enable the use of materials having the same buffer layer. For example, antimonide quantum wells have been used in Schottky-barrier p-FETs with good DC and microwave performance. See M. Radosavljevic, T. Ashley, A. Andreev, S. D. Coomber, G. Dewey, M. T. Emeny, M. Fearn, D. G. Hayes, K. P. Hilton, M. K. Hudait, R. Jefferies, T. Martin, R. Pillarisetty, W. Rachmady, T. Rakshit, S. J. Smith, M. J. Uren, D. J. Wallis, P. J. Wilding, and R. Chau, “High-performance 40 nm gate length InSb p-channel compressively strained quantum well field effect transistors for low-power (VCC=0.5V) logic applications,” IEEE International Electron Devices Meeting 2008, Technical Digest, 727-730; see also J. B. Boos, B. R. Bennett, N. A. Papanicolaou, M. G. Ancona, J. G. Champlain, R. Bass, and B. V. Shanabrook, “High mobility p-channel HFETs using strained Sb-based materials,” Electronics Letters 43, 834-835 (2007).
Work on enhancing the hole mobilities of such materials for p-FET applications has been encouraging. Confinement and biaxial strain have been used to lift the heavy-hole/light-hole degeneracy, reduce the effective mass, and enhance the hole mobility, see B. R. Bennett, M. G. Ancona, and J. B. Boos, “Compound Semiconductors for Low-Power p-Channel Field-Effect Transistors,” MRS Bulletin 34, 530-536 (2009); and A. Nainani, B. R. Bennett, J. B. Boos, M. G. Ancona, and K. C. Saraswat, “InxGa1−xSb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design,” Journal of Applied Physics 111 (2012), with room-temperature hole mobilities as high as 1100-1500 cm2/V s for InSb, GaSb, and InGaSb having been reported. See Radosavljevic, supra; see also B. R. Bennett, M. G. Ancona, J. B. Boos, C. B. Canedy, and S. A. Khan, “Strained GaSb/AlAsSb quantum wells for p-channel field-effect transistors,” Journal of Crystal Growth 311, 47-53 (2008); B. R. Bennett, T. F. Chick, M. G. Ancona, and J. B. Boos, “Enhanced hole mobility and density in GaSb quantum wells,” Solid-State Electronics 79, 274-280 (2013); V. Tokranov, P. Nagaiah, M. Yakimov, R. J. Matyi, and S. Oktyabrsky, “AlGaAsSb superlattice buffer layer for p-channel GaSb quantum well on GaAs substrate,” Journal of Crystal Growth 323, 35-38 (2011); and B. R. Bennett, M. G. Ancona, J. B. Boos, and B. V. Shanabrook, “Mobility enhancement in strained p-InGaSb quantum wells,” Applied Physics Letters 91, 042104 (2007).
The use of antimonide/arsenide heterostructures for n-FETs and other electronic devices has also been explored. See B. R. Bennett, R. Magno, J. B. Boos, W. Kruppa, and M. G. Ancona, “Antimonide-Based Compound Semiconductors for Electronic Devices: A Review,” Solid-State Electronics 49, 1875-1895 (2005).
(In)GaSb-channel MOSFETs have also been fabricated. Such MOSFETs are attractive because they have a much lower gate leakage current, which is a critical requirement in low-power logic circuits. See A. Nainani, T. Irisawa, Z. Yuan, B. R. Bennett, J. B. Boos, Y. Nishi, and K. C. Saraswat, “Optimization of the Al2O3/GaSb Interface and a High-Mobility GaSb pMOSFET,” IEEE Transactions on Electron Devices 58, 3407-3415 (2011); A. Nainani, Z. Yuan, T. Krishnamohan, B. R. Bennett, J. B. Boos, M. Reason, M. G. Ancona, Y. Nishi, and K. C. Saraswat, “InxGa1−xSb channel p-metal-oxide-semiconductor field effect transistors: Effect of strain and heterostructure design,” Journal of Applied Physics 110 (2011); S. Oktyabrsky, Fundamentals of III-V Semiconductor MOSFETs, 349-378 (2010); and M. Xu, R. S. Wang, and P. D. Ye, “GaSb Inversion-Mode PMOSFETs With Atomic-Layer-Deposited Al2O3 as Gate Dielectric,” IEEE Electron Device Letters 32, 883-885 (2011).
The antimonide heterostructures used for p-FETs have type-I band alignments, with substantial conduction--as well as valence--band offsets. Consequently, a third option for a III-V CMOS is to use antimonide QWs for both n- and p-FETs. For InSb QWs, high-frequency n-FETs have been reported. See T. Ashley, L. Buckle, S. Datta, M. T. Emeny, D. G. Hayes, K. P. Hilton, R. Jefferies, T. Martin, T. Phillips, D. J. Wallis, P. J. Wilding, and R. Chau, “Heterogeneous InSb quantum well transistors on silicon for ultra-high speed, low power logic applications,” Electronics Letters 43, 777-779 (2007).
One potential limitation to InSb QWs for integrated n- and p-FETs is that simulations suggest it may be difficult to attain high ION/IOFF ratios because of the small band gap and band offsets. See M. G. Ancona, B. R. Bennett, and J. B. Boos, “Scaling Projections for Sb-based p-channel FETs,” Solid-State Electronics 54, 1349-1358 (2010).
To address this problem, researchers at the Naval Research Laboratory have proposed the use of the same InGaSb channel for both the n- and p-FETs in a CMOS device. See U.S. Pat. No. 8,461,664 to B. R. Bennett, J. B. Boos, M. G. Ancona, J. G. Champlain, and N. A. Papanicolaou, entitled “n- and p-Channel Field Effect Transistors with Single Quantum Well for Complementary Circuits” (2013); see also B. R. Bennett, M. G. Ancona, J. G. Champlain, N. A. Papanicolaou, and J. B. Boos, “Demonstration of high-mobility electron and hole transport in a single InGaSb well for complementary circuits,” Journal of Crystal Growth 312, 37-40 (2009). However, although high electron mobilities have been achieved, no group has reported a high-performance InGaSb n-FET. Id.; see also L. Desplanque, D. Vignaud, S. Godey, E. Cadio, S. Plissard, X. Wallart, P. Liu, and H. Sellier, “Electronic properties of the high electron mobility Al0.56In0.44Sb/Ga0.5In0.5 Sb heterostructure,” Journal of Applied Physics 108, 043704 (2010); and R. Loesch, R. Aidam, L. Kirste, and A. Leuther, “Molecular beam epitaxial growth of metamorphic AlInSb/GaInSb high-electron-mobility-transistor structures on GaAs substrates for low power and high frequency applications,” Journal of Applied Physics 109, 033706 (2011).
A fourth option is to combine p-channel InGaSb with n-channel InAsSb. See A. Ali, H. Madan, A. Agrawal, I. Ramirez, R. Misra, J. B. Boos, B. R. Bennett, J. Lindemuth, and S. Datta, “Enhancement Mode Antimonide Quantum Well MOSFETs With High Electron Mobility and GHz Small-Signal Switching Performance,” IEEE Electron Device Letters 32, 1689-1691 (2011). In such structures, separate quantum wells are required for the n- and p-channels, but a common buffer layer could be used to prevent mismatches in the coefficients of thermal expansion. See U.S. Pat. No. 7,429,747 to M. K. Hudait, S. Datta, J. T. Kavalieros, M. L. Doczy, and R. S. Chau, entitled “Sb-Based CMOS Devices” (2008).